1. Field of the Invention
The invention relates to packet processing apparatus, to methods of reconfiguring a packet processor, and to methods of using a packet processor.
2. Background Art
It is known to transmit data in packets, each packet having header information as part of the packet, for use in processing the packet. The location and meaning of the header information within each packet is defined by a protocol. Most packet data transmission networks use multiple layers of protocols, in a hierarchy, according to the well known ISO model. Starting with the raw data from a top level application, each protocol adds its own header information to that added previously by preceding (higher) protocols. In the course of transmission through the network, the packet may pass through and be routed, forwarded switched or processed according to information stored in various parts of the packet header, depending on which level of the various levels of protocols, is being used.
Conventionally, in a router or switch operating according to a given one of the protocols, for each incoming packet, particular bits in the header relating to that given protocol are examined. The packet would be routed using those bits and passed to a chosen output port. Dedicated hardware is often used for speed of operation.
New types of protocol processing using different parts of header or payload information with different meanings, are always being proposed, at all different layers, to meet new requirements for e.g. quality of service, billing functions, error handling, grouping of packets, prioritizing, and so on. However, development of appropriate hardware is time consuming, even when groups of programmable logic chips are used, for a number of reasons. Connections between such chips must be defined and fixed, and changes made to the relatively complex logic which is often involved, will often have consequences to other parts of the logic, which are difficult to manage.
Software simulations and verifications of hardware designs can be carried out, but often do not reveal all the problems of a real hardware implementation.
Programmable chips for switching packets of particular protocols are known, e.g. ethernet switching chips, and protocol-specific dedicated router chips. Such router chips can extract destination information from a packet using hardcoded logic to achieve higher speed or throughput. They use a routing table whose entries can programmed from an external host.
A chipset produced by Obtek provides multiprotocol packet routing. A programmable filter examines the contents of each incoming packet to derive the buried protocols and retrieve source and destination addresses. The filter passes a packet descriptor to a routing systems control chip which manages memory allocation, input and output queues.
This filter is programmable using a proprietary language, a rule-based language which enables a programmer to define actions to be taken according to recognition of bits in a packet. As the filter's active structure parses and processes the unknown incoming packet, it is capable of activating other processors (including a host) or special hardware (for very high performance) to perform concurrent and supporting tasks.